Solar cells are photovoltaic (PV) devices that convert sunlight directly into electrical power. The most common solar cell material is silicon, which is in the form of single or polycrystalline wafers. However, the cost of electricity generated using silicon-based solar cells is higher than the cost of electricity generated by the more traditional methods. Therefore, since early 1970's there has been an effort to reduce cost of solar cells for terrestrial use. One way of reducing the cost of solar cells is to develop low-cost thin film growth techniques that can deposit solar-cell-quality absorber materials on large area substrates and to fabricate these devices using high-throughput, low-cost methods.
Group IBIIIAVIA compound semiconductors comprising some of the Group IB (Cu, Ag, Au), Group IIIA (B, Al, Ga, In, Tl) and Group VIA (O, S, Se, Te, Po) materials or elements of the periodic table are excellent absorber materials for thin film solar cell structures. Especially, compounds of Cu, In, Ga, Se and S which are generally referred to as CIGS(S), or Cu(In,Ga)(S,Se)2 or CuIn1-xGax (SySe1-y)k, where 0≦x≦1, 0≦y≦1 and k is approximately 2, have already been employed in solar cell structures that yielded conversion efficiencies approaching 20%. Absorbers containing Group IIIA element Al and/or Group VIA element Te also showed promise. Therefore, in summary, compounds containing: i) Cu from Group IB, ii) at least one of In, Ga, and Al from Group IIIA, and iii) at least one of S, Se, and Te from Group VIA, are of great interest for solar cell applications.
The structure of a conventional Group IBIIIAVIA compound photovoltaic cell such as a Cu(In,Ga,Al)(S,Se,Te)2 thin film solar cell is shown in FIG. 1. The device 10 is fabricated on a substrate 11, such as a sheet of glass, a sheet of metal, an insulating foil or web, or a conductive foil or web. The absorber film 12, which comprises a material in the family of Cu(In,Ga,Al)(S,Se,Te)2, is grown over a conductive layer 13, which is previously deposited on the substrate 11 and which acts as the electrical contact to the device. The structure comprising the substrate 11 and the conductive layer 13 is the base 10A. Various conductive layers comprising Mo, Ta, W, and Ti etc. have been used in the solar cell structure of FIG. 1. If the substrate itself is a properly selected conductive material, it is possible not to use a conductive layer 13, since the substrate 11 may then be used as the ohmic contact to the device. After the absorber film 12 is grown on the surface 13A of the conductive layer 13, a transparent layer 14 such as a CdS, ZnO or CdS/ZnO stack is formed on the absorber film. Radiation 15 enters the device through the transparent layer 14. Metallic grids (not shown) may also be deposited over the transparent layer 14 to reduce the effective series resistance of the device. The preferred electrical type of the absorber film 12 is p-type, and the preferred electrical type of the transparent layer 14 is n-type. However, an n-type absorber and a p-type window layer can also be utilized. The preferred device structure of FIG. 1 is called a “substrate-type” structure. A “superstrate-type” structure can also be constructed by depositing a transparent conductive layer on a transparent superstrate such as glass or transparent polymeric foil, and then depositing the Cu(In,Ga,Al)(S,Se,Te)2 absorber film, and finally forming an ohmic contact to the device by a conductive layer. In this superstrate structure light enters the device from the transparent superstrate side. A variety of materials, deposited by a variety of methods, can be used to provide the various layers of the device shown in FIG. 1.
In a thin film solar cell employing a Group IBIIIAVIA compound absorber, the cell efficiency is a strong function of the molar ratio of IB/IIIA. If there are more than one Group IIIA materials in the composition, the relative amounts or molar ratios of these IIIA elements also affect the properties. For a Cu(In,Ga)(S,Se)2 absorber layer, for example, the efficiency of the device is a function of the molar ratio of Cu/(In+Ga). Furthermore, some of the important parameters of the cell, such as its open circuit voltage, short circuit current and fill factor vary with the molar ratio of the IIIA elements, i.e. the Ga/(Ga+In) molar ratio. In general, for good device performance Cu/(In+Ga) molar ratio is kept at around or below 1.0. As the Ga/(Ga+In) molar ratio increases, on the other hand, the optical bandgap of the absorber layer increases and therefore the open circuit voltage of the solar cell increases while the short circuit current typically may decrease. It is important for a thin film deposition process to have the capability of controlling both the molar ratio of IB/IIIA, and the molar ratios of the Group IIIA components in the composition. It should be noted that although the chemical formula is often written as Cu(In,Ga)(S,Se)2, a more accurate formula for the compound is Cu(In,Ga)(S,Se)k, where k is typically close to 2 but may not be exactly 2. For simplicity we will continue to use the value of k as 2. It should be further noted that the notation “Cu(X,Y)” in the chemical formula means all chemical compositions of X and Y from (X=0% and Y=100%) to (X=100% and Y=0%). For example, Cu(In,Ga) means all compositions from CuIn to CuGa. Similarly, Cu(In,Ga)(S,Se)2 means the whole family of compounds with Ga/(Ga+In) molar ratio varying from 0 to 1, and Se/(Se+S) molar ratio varying from 0 to 1.
The first technique that yielded high-quality Cu(In,Ga)Se2 films for solar cell fabrication was co-evaporation of Cu, In, Ga and Se onto a heated substrate in a vacuum chamber. However, low materials utilization, high cost of equipment, difficulties faced in large area deposition and relatively low throughput are some of the challenges faced in commercialization of the co-evaporation approach.
Another technique for growing Cu(In,Ga)(S,Se)2 type compound thin films for solar cell applications is a two-stage process where metallic components of the Cu(In,Ga)(S,Se)2 material, i.e. Cu, In and/or Ga are first deposited onto a substrate as a metallic precursor layer, and then reacted with S and/or Se in a high temperature annealing process. For example, for CuInSe2 growth, thin layers of Cu and In are first deposited on a substrate and then this stacked precursor layer is reacted with Se (selenization) at elevated temperature. If the reaction atmosphere also contains sulfur (sulfidation), then a CuIn(S,Se)2 or CISS layer can be grown. It is also possible to selenize and then sulfidize the Cu/In precursor to obtain a CISS absorber. Addition of Ga in the precursor layer, i.e. use of a stack such as a Cu/In/Ga stacked film metallic precursor, allows the growth of a Cu(In,Ga)(S,Se)2 or CIGSS absorber. It should be noted that we refer to Cu, In and Ga as the metallic components of the CIGS(S) compound whereas Se and S are non-metallic components. Selenium and S are sometimes referred to as “semi-metals” in their crystalline form. In publications, the crystalline form of Se may also be called “metallic Se”.
Sputtering and evaporation techniques have been used in prior art approaches to deposit the layers containing the Group IB and Group IIIA components of the precursor stacks. In the case of CuInSe2 growth, for example, Cu and In layers were sequentially sputter-deposited on a substrate and then the stacked film was heated in the presence of gas containing Se at elevated temperature for times typically longer than about 30 minutes, as described in U.S. Pat. No. 4,798,660. More recently U.S. Pat. No. 6,048,442 disclosed a method comprising sputter-depositing a stacked precursor film comprising a Cu—Ga alloy layer and an In layer to form a Cu—Ga/In stack on a metallic back electrode layer and then reacting this precursor stack film with one of Se and S to form the absorber layer. U.S. Pat. No. 6,092,669 described sputtering-based equipment for producing such absorber layers.
Two-stage processing approach may also employ stacked precursor layers comprising Group VIA materials. For example, a Cu(In,Ga)Se2 or CIGS film may be obtained by depositing In—Ga-selenide and Cu-selenide layers in a stacked manner and reacting them in presence of Se. Similarly, stacks comprising Group VIA materials and metallic components may also be used. In—Ga-selenide/Cu stack, for example, may be reacted in presence of Se to form CIGS. Stacks comprising metallic elements as well as Group VIA materials in discrete layers may also be used. Selenium may be deposited on a metallic precursor film comprising Cu, In and/or Ga through various approaches to form stacks such as Cu/In/Ga/Se, Cu—Ga/In/Se, etc. One approach for Se layer formation is evaporation as described by J. Palm et al. (“CIS module pilot processing applying concurrent rapid selenization and sulfurization of large area thin film precursors”, Thin Solid Films, vol. 431-432, p. 514, 2003). In their work these authors described preparation of a precursor stack by sputter deposition of a Cu—Ga/In metallic precursor layer followed by evaporation of Se over the In surface. The precursor stack thus formed had a structure of Cu—Ga/In/Se. After rapid thermal annealing or processing (RTP) of the precursor stack and further reaction with S, these researchers reported formation of Cu(In,Ga)(Se,S)2 or CIGS(S) absorber layer.
Evaporation is a relatively high cost technique to employ in large scale manufacturing of absorbers intended for low cost solar cell fabrication. Potentially lower cost techniques such as electroplating have been reported for Se deposition. For example, A. Von Hippel et al. (“Electrodeposition of Se”, U.S. Pat. No. 2,649,409, 1953) disclosed that metallic Se may be electroplated using specialized electrolytes and high bath temperatures. Typically Se deposits or films obtained from low temperature baths are of amorphous nature and have high resistivity, which may be higher than 104 ohm-cm. Such high resistivity amorphous layers may not be plated to thicknesses much above about 500 nm unless special care is taken.
Since amorphous Se layers are of high resistivity they can only be deposited to thicknesses of above about 500 nm at low current densities, which may be typically less than about 3 mA/cm2. Otherwise, at higher current densities the high resistivity Se film may electrically break down giving rise to defects and non-uniform coating. A. Graham et al. (“Electrodeposition of amorphous Se”, J. Electrochemical Society, vol. 106, p. 651, 1959) have plated 30000 nm thick amorphous Se layers out of special electrolytes at current densities of 0.5-2 mA/cm2. Drawbacks of their technique included short lifetime of the baths as stated by the researchers and the low current densities which would require plating times in the order of 7-24 hours for the deposited layers.
Some information about potential application of electrodeposited Se layers for CIGS absorber formation has also been also published. One specific method published involves depositing a metallic precursor comprising Cu and In on a substrate and then electroplating a Se layer over the Cu/In layer to form a Cu/In/Se stack. This stack may then be heated up to form a CuInSe2 absorber. It should be noted that since CIGS(S) type solar cell absorbers are typically 1-2 um thick, formation of these absorbers require at least about 700 nm, preferably more than 1000 nm thick Se layer. Therefore, any electroplating technique that will be used to deposit Se layer for CIGS(S) type absorber formation is required to provide 700-2000 nm thick Se layer depending on the thickness of the absorber and the details of the absorber formation process. In many CIGS growth approaches, such as RTP, excess Se is needed (typically 20-50% more than the amount needed to form the compound) to assure full reaction of the metallic components of the compound with relatively volatile Se, some of which may evaporate away from the film surface during heating.
As the brief review above demonstrates, thick Se layers may be electroplated on selected substrates in the form of metallic Se, which has a lower resistivity than the amorphous Se. However, plating of metallic Se requires use of high temperature baths and highly acidic bath formulations which are not suitable for large scale production. These baths also have stability problem. If amorphous Se is electroplated out of simple baths, then deposition of relatively thick layers require low plating current densities, typically lower than 2 mA/cm2, and deposition times that may vary from 30 minutes to several hours. In prior art work, several attempts were made to increase the deposition rate and thickness of the electroplated Se layers. One such approach involved illumination of the photoconductive amorphous Se layer during its deposition on the substrate (H. Fritz et al., “A new electrochemical method for selenization of stacked CuIn layers and preparation of CIS by thermal annealing”, Thin Solid Films, vol. 247, p. 129, 1994). Through illumination, the effective resistivity of the Se film was reduced to allow higher deposition current densities.
As the review of prior art shows there is a need to develop electroplating techniques that can deposit Group VIA materials comprising Se with a thickness greater than about 500 nm using simple electrolytes and short deposition times.